Builder ffmpeg-solaris10-sparc Build #10946

Results:

Failed shell_2 shell_3 shell_4 shell_5

SourceStamp:

BuildSlave:

Reason:

The SingleBranchScheduler scheduler named 'schedule-ffmpeg-solaris10-sparc' triggered this build

Steps and Logfiles:

1. git update ( 9 secs )
   1. stdio
2. shell 'gsed -i ...' ( 0 secs )
   1. stdio
3. shell_1 'gsed -i ...' ( 0 secs )
   1. stdio
4. shell_2 'gsed -i ...' failed ( 0 secs )
   1. stdio
5. shell_3 './configure --samples="../../../ffmpeg/fate-suite" ...' failed ( 6 secs )
   1. stdio
   2. config.log
6. shell_4 'gmake fate-rsync' failed ( 0 secs )
   1. stdio
7. shell_5 '../../../ffmpeg/fate.sh ../../../ffmpeg/fate_config.sh' failed ( 1 secs )
   1. stdio
   2. configure.log
   3. compile.log
   4. test.log

Build Properties:

Forced Build Properties:

Responsible Users:

1. Rémi Denis-Courmont

   remiohnoyoudont@remlab.net

Timing:

All Changes:

:

1. Change #198009

   Category	ffmpeg
   Changed by	Rémi Denis-Courmont <remiohnoyoudont@remlab.net>
   Changed at	Wed 22 May 2024 18:15:39
   Repository	https://git.ffmpeg.org/ffmpeg.git
   Project	ffmpeg
   Branch	master
   Revision	910d281b215720dc831486aba36e31528b30b6bc

   Comments

   lavc/h263dsp: R-V V {h,v}_loop_filter
   Since the horizontal and vertical filters are identical except for a
   transposition, this uses a common subprocedure with an ad-hoc ABI.
   To preserve return-address stack prediction, a link register has to be
   used (c.f. the "Control Transfer Instructions" from the
   RISC-V ISA Manual). The alternate/temporary link register T0 is used
   here, so that the normal RA is preserved (something Arm cannot do!).
   
   To load the strength value based on `qscale`, the shortest possible
   and PIC-compatible sequence is used: AUIPC; ADD; LBU. The classic
   LLA; ADD; LBU sequence would add one more instruction since LLA is a
   convenience alias for AUIPC; ADDI. To ensure that this trick works,
   relocation relaxation is disabled.
   
   To implement the two signed divisions by a power of two toward zero:
    (x / (1 << SHIFT))
   the code relies on the small range of integers involved, computing:
    (x + (x >> (16 - SHIFT))) >> SHIFT
   rather than the more general:
    (x + ((x >> (16 - 1)) & ((1 << SHIFT) - 1))) >> SHIFT
   Thus one ANDI instruction is avoided.
   
   T-Head C908:
   h263dsp.h_loop_filter_c:       228.2
   h263dsp.h_loop_filter_rvv_i32: 144.0
   h263dsp.v_loop_filter_c:       242.7
   h263dsp.v_loop_filter_rvv_i32: 114.0
   (C is probably worse in real use due to less predictible branches.)

   Changed files

   • libavcodec/h263dsp.c
   • libavcodec/h263dsp.h
   • libavcodec/riscv/Makefile
   • libavcodec/riscv/h263dsp_init.c
   • libavcodec/riscv/h263dsp_rvv.S